An effective two-pattern test generator for Arithmetic BIST

This item is provided by the institution :
Technological Educational Institute of Athens
Repository :
Ypatia - Institutional Repository
see the original item page
in the repository's web site and access all digital files if the item*

2013 (EN)
An effective two-pattern test generator for Arithmetic BIST (EN)

Ευσταθίου, Κωνσταντίνος Η. (EL)
Αντωνοπούλου, Σωτηρία-Ήρα (EL)
Βογιατζής, Ιωάννης (EL)
Μηλιδώνης, Αθανάσιος (EL)

Τεχνολογικό Εκπαιδευτικό Ίδρυμα Αθήνας.Σχολή Τεχνολογικών Εφαρμογών.Τμήμα Μηχανικών Πληροφορικής (EL)

Built-In Self Test (BIST) techniques perform test pattern generation and response verification operations on-chip. In Arithmetic BIST, modules that commonly exist in datapaths (accumulators, counters, etc.) are utilized to perform the above-mentioned operations. In order to detect faults that occur into current CMOS circuits, two-pattern tests are required. Furthermore, delay testing, commonly used to assure correct temporal circuit operation at clock speed requires two-pattern tests. In this paper a novel two-pattern test generator for Arithmetic BIST is presented. Its hardware implementation compares favorably to the techniques that have been presented in the literature. Application of the proposed scheme for the two-pattern testing of ROM modules revealed that the testing of small-to-medium size ROMs is completed within reasonable time and with negligible hardware overhead. (EN)


Analog CMOS ολοκληρωμένα κυκλώματα (EN)
Built-In Self Test (BIST) (EN)
Δύο-πρότυπο γεννήτρια δοκιμής (EN)
Analog CMOS integrated circuits (EN)
Two-pattern test generator (EN)

ΤΕΙ Αθήνας (EL)
Technological Educational Institute of Athens (EN)

Computers & Electrical Engineering (EN)




N/A (EN)

*Institutions are responsible for keeping their URLs functional (digital file, item page in repository site)