A CLASS OF SYSTOLIC SERIAL-PARALLEL MULTIPLIERS
(EN)
CARAISCOS, CG
(EN)
PEKMESTZI, KZ
(EN)
A scheme for a fully-systolic bit-serial multiplier is presented, based on merging two adjacent cells of an existing semi-systolic multiplier in a single new cell. The multiplier has immediate response and high bit-throughput, limited by the propagation delay of one gated full adder and a latch. A way to increase the word-throughput, while retaining systolicity, is also presented.
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