Systolic frequency dividers/counters

 
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Journal part (EN)
Scientific article (EN)
1994 (EN)
Systolic frequency dividers/counters (EN)
Pekmestzi, KZ (EN)
Thanasouras, N (EN)
The operation of systolic counters, based on the pipelining of the conventional binary counters, is examined. The application of these circuits in the implementation of frequency dividers/counters is also presented. The proposed systolic counters have small circuit complexity and permit very high speed operation. (EN)
journalArticle (EN)
Computational methods (EN)
Bit error rate (EN)
Pipeline processing systems (EN)
Engineering, Electrical & Electronic (EN)
Frequency dividing circuits (EN)
State assignment (EN)
Computational complexity (EN)
Response time (computer systems) (EN)
Counting circuits (EN)
High Speed (EN)
Systolic counters (EN)
Binary codes (EN)
Computer architecture (EN)
Systolic arrays (EN)
Clock pulses (EN)
Flip flop circuits (EN)
Circuit Complexity (EN)
Binary sequences (EN)
National Technical University of Athens
Digital Library of National Technical University of Athens | Dspace@NTUA
Κεντρική Βιβλιοθήκη Ε.Μ.Π.
Ιδρυματικό Αποθετήριο
Δημοσιεύσεις μελών Δ.Ε.Π. σε περιοδικά
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing (EN)
English
1994 (EN)
http://hdl.handle.net/123456789/11366
11 (EN)
775 (EN)
776 (EN)
1057-7130 (EN)
ISI:A1994PV34500010 (EN)
10.1109/82.331551 (EN)
41 (EN)
IEEE, Piscataway, NJ, United States (EN)



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