Modelling MOSFET gate length variability for future technology nodes

 
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Technological Educational Institute of Athens
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2008 (EN)
Modelling MOSFET gate length variability for future technology nodes (EN)

Πάτσης, Γεώργιος (EL)

N/A (EN)

Gate length variability due to intra or inter die variations can lead to considerable mismatch between devices even inside the same chip. This variability has to be considered in detail and new device models should be developed, aiming in modelling its effects on the electrical characteristics devices. In this work the Philips MM11 MOSFET model is extended to incorporate gate length variability. This is introduced by dividing the device width into sub-units following a Gaussian gate length distribution, with appropriate line-width roughness. The combined model is used to quantify the drain-source current in terms of gate line-width roughness. The model is coded in VHDL-AMS in order to be used for simulation of circuit behaviour inside the framework of appropriate system simulation software such as Ansfoft's Simplorer. (EN)

journalArticle

Τεχνολογικοί κόμβοι (EN)
Technology nodes (EN)
Μικροηλεκτρονική (EN)
Microelectronics (EN)
Ολοκληρωμένο σύστημα (EN)
Chip (EN)

ΤΕΙ Αθήνας (EL)
Technological Educational Institute of Athens (EN)

Physica status solidi (EN)

English

2008-09-17

DOI: 10.1002/pssa.200780174

Wiley (EN)



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