Experiments and simulations suggest that low-molecular-weight resist materials could result in low line-edge roughness (LER) which is a critical parameter for the forthcoming technology nodes. Two positive molecular resist architectures are modeled with a stochastic lithography simulator and their LER behavior is quantified. The corresponding LER values obtained are less than 1nm, suggesting that such materials are promising for the fabrication of devices even down to the 32 nm node. Two-dimensional lattices with the molecular resist architectures are created and combined with the stochastic lithography simulator and a simple etching modeling algorithm, in order to test the transferred line-width roughness (LWR) on the gate region of the pMOS and nMOS transistors of an inverter cell designed with 40 nm nominal gate length. The role of the molecular resist architecture on the final LWR of transistor gate is discussed.
(EN)
