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An FPGA-based sudoku solver based on simulated annealing methods

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Technical University of Crete   

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An FPGA-based sudoku solver based on simulated annealing methods (EN)
Σωτηριαδης Ευριπιδης (EL)
Μαλακωνακης Παυλος (EL)
Δολλας Αποστολος (EL)
Σμερδης Μιλτιαδης (EL)
Dollas Apostolos (EN)
Malakonakis Pavlos (EN)
Smerdis Miltiadis (EN)
Sotiriadis Evripidis (EN)
other
conferenceItem
2009
The Sudoku simulated annealing solver -SSAS is a probabilistic Sudoku solver. The general design is capable of solving a Sudoku board of order up to fifteen (15 × 15 × 15 × 15). It has been designed and fully implemented on a Xilinx Virtex II Pro - based Digilent XUP board. The solver has a serial-port interface to download problems and upload results to a personal computer, according to the specifications of the relevant competition of the 2009 International Conference on Field Programmable Technology (FPT). The SSAS has solved in actual hardware Sudoku puzzles of up to order 12 within the competition-imposed time limits. (EN)
Field programmable logic arrays,FPGAs,field programmable gate arrays,field programmable logic arrays,fpgas (EN)
International Conference on Field-Programmable Technology (EL)
English
Institute of Electrical and Electronics Engineers (EN)
Πολυτεχνείο Κρήτης (EL)
Technical University of Crete (EN)
Technical University of Crete
Institutional Repository Technical University of Crete
School of Chemical and Environmental Engineering - Journal Publications



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