Validation of design rules taking into account fine details such as line-edge roughness, and full chip layout simulation for design inconsistencies, before actual fabrication, are among the main objectives of current software assisted metrology tools. Line-edge roughness quantification should accompany critical dimension (CD) measurements since it could be a large fraction of the total CD budget. A detailed simulation and metrology approach of line-edge roughness quantification versus the length scales in a layout are presented in this work using a combination of electron beam simulation for the exposure part, and stochastic simulations for the modeling of resist film, postexposure bake, and resist dissolution. The method is applied also on a test layout with critical dimension of 200nm and the resulted simulation and scanning electron microscopy images are compared with the aid of a pattern matching algorithm which enables the identification of the desired layout for metrology on a complex layout containing many printed features.
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