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Designing coarse-grain reconfigurable architectures by inlining flexibility into custom arithmetic data-paths

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National Technical University of Athens   

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Designing coarse-grain reconfigurable architectures by inlining flexibility into custom arithmetic data-paths (EN)
Economakos, G (EN)
Xydis, S (EN)
Pekmestzi, K (EN)
journalArticle (EN)
2014-03-01T01:30:08Z
2009 (EN)
This paper introduces a design technique for coarse-grained reconfigurable architectures targeting digital signal processing (DSP) applications. The design procedure is analyzed in detail and an area-time-power efficient reconfigurable kernel architecture is presented. The proposed technique inlines flexibility into custom carry-save (CS) arithmetic datapaths exploiting a stable and canonical interconnection scheme. The canonical interconnection is revealed by a transformation, called uniformity transformation, imposed on the basic architectures of CS-multipliers and CS-chain-adders/subtractors. Experimental results including quantitative and qualitative comparisons with existing reconfigurable arithmetic cores and exploration results of the proposed reconfigurable architecture are provided. (C) 2009 Elsevier B.V. All rights reserved. (EN)
Engineering, Electrical & Electronic (EN)
Computer Science, Hardware & Architecture (EN)
Canonical interconnection (EN)
Array multiplier (EN)
Carry-save arithmetic (EN)
Frequency multiplying circuits (EN)
Digital signal processing (EN)
Chain addition (EN)
Signal processing (EN)
Coarse-grain reconfigurable architectures (EN)
Flexibility inlining (EN)
Integration, the VLSI Journal (EN)
English
ELSEVIER SCIENCE BV (EN)
National Technical University of Athens
Digital Library of National Technical University of Athens | Dspace@NTUA
Κεντρική Βιβλιοθήκη Ε.Μ.Π.
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