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High performance and area efficient flexible dsp datapath synthesis

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National Technical University of Athens   

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High performance and area efficient flexible dsp datapath synthesis (EN)
Economakos, G (EN)
Soudris, D (EN)
Xydis, S (EN)
Pekmestzi, K (EN)
journalArticle (EN)
2014-03-01T01:35:47Z
2011 (EN)
This paper presents a new methodology for the synthesis of high performance flexible datapaths, targeting computationally intensive digital signal processing kernels of embedded applications. The proposed methodology is based on a novel coarse-grained reconfigurable/flexible architectural template, which enables the combined exploitation of the horizontal and vertical parallelism along with the operation chaining opportunities found in the application's behavioral description. Efficient synthesis techniques exploiting these architectural optimization concepts from a higher level of abstraction are presented and analyzed. Extensive experimentation showed average latency and area reductions up to 33.9% and 53.9%, respectively, and higher hardware area utilization, compared to previously published high performance coarse-grained reconfigurable datapaths. © 2006 IEEE. (EN)
Engineering, Electrical & Electronic (EN)
Computer Science, Hardware & Architecture (EN)
Area reduction (EN)
Architecture (EN)
Embedded application (EN)
high level synthesis (EN)
Coarse grained reconfigurable architecture (EN)
Level of abstraction (EN)
Re-configurable (EN)
Reconfigurable hardware (EN)
Area utilization (EN)
Optimization (EN)
Data paths (EN)
Coarse-grained reconfigurable architectures (EN)
Area efficient (EN)
Behavioral descriptions (EN)
Signal processing (EN)
Coarse-grained (EN)
datapath optimization (EN)
Efficient synthesis (EN)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (EN)
English
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC (EN)
National Technical University of Athens
Digital Library of National Technical University of Athens | Dspace@NTUA
Κεντρική Βιβλιοθήκη Ε.Μ.Π.
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