Σημασιολογικός εμπλουτισμός/ομογενοποίηση από το EKT
Design of a High-Speed UART VLSI Library Cell
Σχεδίαση Ενός Υψηλής Ταχύτητας UART Δομικού Στοιχείου για Βιβλιοθήκες Ολοκληρωμένων Κυκλωμάτων VLSI
We present the sampling and decoding algorithm and the VLSI implementation of a high-speed UART (Universal Asynchronous Receiver- Transmitter) library cell to be used in custom or semi-custom VLSI chip designs. Our approach to data recovery, which is based on signal preprocessing and an innovative decoding algorithm, operates with as few as 2 samples per bit time, thus achieving a high communication rate. Using a clock of frequency 'f' MHz, this UART can transmit and receive at a rate of up to 'f' Mbits/s, without any internal multiplication of the clock frequency. The current design, that was submitted for fabrication operates at data rates up to 25 Mbits/s (ES2 1.5 um CMOS standard cell technology), while extensive simulations for a higher performance technology (1 um gate-array) verify that our cell operates at data rates up to 60 Mbits/s. We are currently performing post-fabrication testing, and some preliminary results show that the prototypes operate succesfully at the data rate of 20 MHz. The resulting cell is small and flexible, making it suitable to be used as a building block in chip designs. It can serve as an interface between serial asynchronous communication links, or as a building block for fast and inexpensive networks.