A new wiring architectUre for parallel processing applications

 
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Journal part (EN)
Scientific article (EN)
1990 (EN)
A new wiring architectUre for parallel processing applications (EN)
Papananos, Y (EN)
In this paper, a new architecture for the connection between processing elements in a processing array is proposed. Each PE must be connected to all PEs in a window of size n x n around it. The model is simple and elegant and the introduced reduction in wiring complexity is drastic: it becomes O(n) instead of O(n2) as it would be in the general simple case where all PEs are connected directly to the central PE of the window. On the other hand, the appropriate hardware for the implementation of the proposed technique is very little compared to the whole PE. Further, the utilization factor of the communication channels is evaluated, while a model for the implementation of the PE for a particular algorithm, is proposed, along with the extension of the introduced wiring model in fully interconnected neural networks. © 1990 Elsevier Science Publishers B.V. (EN)
journalArticle (EN)
Processing array (EN)
Computer Architecture (EN)
VLSI (EN)
neural networks (EN)
Engineering, Electrical & Electronic (EN)
Neural Networks (EN)
Computer Systems, Digital - Parallel Processing (EN)
wiring model (EN)
Switched Capacitor Circuits (EN)
switched-capacitor circuits (EN)
Computer Science, Hardware & Architecture (EN)
Wiring Models (EN)
Processing Arrays (EN)
National Technical University of Athens
Digital Library of National Technical University of Athens | Dspace@NTUA
Κεντρική Βιβλιοθήκη Ε.Μ.Π.
Ιδρυματικό Αποθετήριο
Δημοσιεύσεις μελών Δ.Ε.Π. σε περιοδικά
Integration, the VLSI Journal (EN)
English
1990 (EN)
http://hdl.handle.net/123456789/10161
0167-9260 (EN)
88 (EN)
1 (EN)
71 (EN)
ISI:A1990EB21500006 (EN)
10 (EN)
ELSEVIER SCIENCE BV (EN)



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