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A bit-interleaved systolic architecture for a high-speed RSA system

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National Technical University of Athens   

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A bit-interleaved systolic architecture for a high-speed RSA system (EN)
Moshopoulos, NK (EN)
Pekmestzi, KZ (EN)
journalArticle (EN)
2014-03-01T01:15:58Z
2001 (EN)
A new systolic serial-parallel scheme that implements the Montgomery multiplier is presented. The serial input of this multiplier consists of two sets of data that enter in a bit-interleaved form. The results are also derived in the same form. The design, with minor modifications, can be used for the implementation of the RSA algorithm by realizing the square-and-multiply algorithm. The circuit yields the lowest hardware complexity reported and permits high-speed operation with 100% efficiency. (C) 2001 Elsevier Science B.V. All rights reserved. (EN)
Engineering, Electrical & Electronic (EN)
Computer Science, Hardware & Architecture (EN)
RSA (EN)
Systolic circuits (EN)
Algorithms (EN)
Computer hardware (EN)
Logic circuits (EN)
Montgomery (EN)
Square and multiply (EN)
Systolic circuit (EN)
Multiplying circuits (EN)
Integration, the VLSI Journal (EN)
English
ELSEVIER SCIENCE BV (EN)
National Technical University of Athens
Digital Library of National Technical University of Athens | Dspace@NTUA
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